This invention relates to a semiconductor memory device.
A semiconductor memory device, such as a DRAM (Dynamic Random Access Memory), has been recently developed. In such a semiconductor memory device, a command signal, an address signal, and a data signal are input and output in synchronism with an external reference clock signal.
Herein, disclosure has been made about the DRAM to enhance a yield in 1995 ISSCC DIGEST of Technical Papers, pages 254-255. In the above DRAM, one memory chip is structured by a plurality of flexible macro chips. Herein, the flexible macro chip may be called a flexible macro or a sub-chip. In the flexible macro chip, the function can be changed by cutting fuses.
Conventionally, the DRAM of 1 G bit is generally structured by the use of four flexible macro chips. In this event, one of the flexible macro chips is given the external reference clock signal. The external reference clock signal is distributed into the respective flexible macro chips as internal reference clock signals on the basis of a tree structure. Herein, the tree structure is formed by a plurality of clock buffers. In this tree structure, a clock input first stage circuit is arranged in one of the flexible macro chips.
As mentioned before, the above DRAM adopts the flexible multi-macro system. Consequently, each of the flexible macro chips must normally operate even when the flexible macro chip is placed at any positions in the memory chip. Therefore, although all of the clock buffers not may always be used, unused buffers may be inactivated in response to signals which are determined by cutting the fuses.
Further, a command input first stage circuit is arranged in each of the flexible macro chips. The command input first stage circuit is driven by the internal reference clock signal. Namely, the above internal reference clock signal is given to the command input first stage circuit to input the command signal and the address signal in synchronism with the external reference clock signal.
The command signal is given to the command input first stage circuit in each of the flexible macro chips. The command signal is sequentially supplied to the buffers along a tree structure.
In this case, when the internal clock signal is always operated, a standby current is inevitably increased. To this end, a "low" level of a chip enable signal is detected at a rise clock of the external reference clock signal. Thereby, the chip is activated and thereafter, the internal reference clock signal is operated.
Specifically, a first flip-flop circuit is provided to latch the detection state of the chip enable signal. Consequently, the internal reference clock signal of a first cycle is operated after the output node of the first flip-flop circuit is put into a "low" level. Therefore, the width of the internal reference clock signal of the first cycle inevitably becomes narrow with a reverse time of the first flip-flop as compared to the width of the internal clock signal of the second cycle and later.
In the above conventional example, when the command input first stage circuit is driven by the use of the internal reference clock signal, a signal path between the clock input first stage circuit and each of the clock buffers in each macro has large parastic resistance and capacitance. This causes a bottle-neck for achieving a minimum cycle time. Herein, if a flip-flop circuit is arranged in the course of the path to eliminate the above bottle neck, the memory chip is enlarged in size and further, the number of access cycles is also increased.
Further, when the internal reference clock signal is generated only in an operation cycle, and the flip-flop is arranged in the clock input first stage circuit to reduce the consumption current during the standby operation, an output of the internal clock signal is delayed, and the clock width of the first clock cycle of the internal clock signal inevitably becomes narrow. Consequently, an operation margin is largely reduced.